1. Field of the Invention
Several unrelated video signals cannot be processed correctly in a single video effects system or displayed on a monitor, without being synchronized first. Namely, each video signal contains line and field synchronization pulses, which are converted to horizontal and vertical deflection signals for a monitor on which the video signal is displayed. The major problem is that the line and field synchronization pulses contained in the different video signals do not occur at the same time. If one of the video signals is used as reference signal, that is the horizontal and vertical deflection signals for a display are derived from this signal, then the following artifacts may appear:
Images that are represented by the other video signals (called the subsignals) will be shifted spatially on the display with regard to the reference signal. PA1 Odd and even video fields in the subsignals may be interchanged which gives rise to visual artifacts like jagged edges and line flicker. PA1 In case line and field frequencies of the video subsignals differ from the reference video signal, then the images represented by these subsignals will crawl across the screen. PA1 Finally, so-called cut-line artifacts may become visible, i.e., different parts of the same displayed image originate from different field/frame periods, which can be rather annoying in moving images where some parts of moving objects seem to lag behind.
2. Description of the Related Art
Traditionally, video synchronizers are built with frame stores that are capable to delay video signals from a few samples to a number of video frame periods. One of these video signals is selected as a reference signal and is not delayed. All samples of the other signals are written into frame stores (one store per signal) as soon as the start of a new frame is detected in these signals. When the start of a new frame in the reference video signal is detected, the read-out of the frame memory is initiated. This way, the vertical synchronization signals contained in the reference and other video signals appear at the same time at the outputs of the synchronization module.
FIG. 1 illustrates synchronization of a video signal with a reference video signal using a FIFO. FIG. 1 shows two independent video signals with their vertical (field) synchronization pulses FP, and the location of read and write pointers in a First-In-First-Out (FIFO) frame store. When a complete frame store is used, all the artifacts mentioned above can be eliminated. At instants SW (at the end of the subsignal (SS) field synchronization pulses FP), writing the subsignal samples a,b,c,d,e,f,g into the FIFO starts. At instants SR (at the end of the synchronization pulses FP of the reference signal RS), reading of the delayed subsignal samples a,b,c,d,e,f,g from the FIFO starts.
It is also possible to use a single field synchronization memory, i.e., the synchronization memory is reduced to one field per input source. In this case, all the above mentioned artifacts are prevented by performing a so-called field inversion, in case video is in the opposite field-phase of the field-phase being displayed on a monitor. This means that an incoming odd field can be locked to the even field that is currently being displayed (being read-out of the field memory) and the even field is locked to the odd field being displayed. To prevent interlace disorder in this case, a field dependent line-delay is applied. See U.S. Pat. Nos. 4,249,198; 4,797,743; and 4,766,506.
FIG. 2 illustrates locking fields of a video input signal to opposite fields of reference, by selectively delaying one field of input signal by one fine, whereby delay is implemented by delaying the read-out of the FIFO. The locking is shown for the case that the read address of the FIFO is manipulated: the displayed image is shifted down by one line. It is also possible to achieve this by manipulating the write address: a line delay in the write will cause upward shifting of the displayed image by one line. The left-hand part of FIG. 2 shows the reference video signal RS, the right-hand part of FIG. 2 shows the video subsignal SS. In each part, the frame line numbers are shown at the left side. The lines 1,3,5,7,9 are in odd fields, while the lines 2,4,6,8,10 are in the even field. The line-numbers 1O, 1E etc., in the fields are shown at the right side. Arrow A1 illustrates that the even field of the subsignal SS locks to the odd field of the reference signal RS. Arrow A2 illustrates that the odd field of the subsignal SS locks to the even field of the reference signal RS. The arrows A3 illustrate the delay of the complete even field of the subsignal SS by one fine to correct the interlace disorder.
A drawback of field inversion is that an additional field-dependent fine delay is necessary which will shift up or down one line whenever a cross occurs in the next field period. This may become annoying when the number of pixels read and write during a field period are very different. E.g., 20% for PAL-NTSC synchronization will give rise to a line shift every 5 field periods, i.e., 10 times per second for display at the PAL standard, which is a visually disturbing artifact.
To prevent cut-lines, i.e., different parts of the image originating from different field periods causing "cut-lines" to appear in moving images, due to crossing of read and write address pointers of the memory in the visible part of the displayed image, a field-skip should be made. This can be done by predicting whenever a "cross" is about to happen in the next field period. By monitoring the number of lines between read and write addresses after each field period, it is possible to predict the time instant that the number of lines between read and write address pointers becomes zero, i.e., a "cross", one field period before it actually occurs. A good remedy to prevent a cut-line is then to stop the writing of the incoming signal at the start of the new field and resume at the start of a next field period. This way, a cross occurs only within the field blanking period.
Conclusions
In the prior art, synchronization of N video sources with a reference video signal, e.g., the display signal, is possible with N video field memories. However, if pixel/line/field rates differ more than just 1% (shifting once every 2 seconds), which may be the case with low-end VCRs, an annoying up-and down shifting results of displayed images due to the necessary field inversion operation. This can only be prevented by using more than just one field memory, i.e., two field memories (one frame).
It is necessary to use a synchronization memory with two independent ports; one for input of the video signal and one for read-out for display, because the pixel rates of display (read-clock) and video input signals (write clocks) are in general not the same.
Field skips should be applied, e.g., stop writing of video input signal during a complete video field period whenever a "cross" of read/write addresses is expected to occur in this field period. Writing can then be resumed in the next field period. In this way, "cut-line" artifacts are prevented.